1. Field of the Invention
The present invention generally relates to watchdog timer circuits, and more particularly a watchdog time circuit that includes two sources for generating reset signals for resetting a watchdog timer.
2. Description of the Prior Art
Watch dog timer circuits including watchdog timers are used to detect runaway of central processing units, microprocessors or the like. Watch dog timer circuits are applied to, for example, data processing systems and communications systems, in which data can be written into a storage unit and read therefrom during a predetermined interval (time window). The watchdog timer circuits detect runaway of the microprocessors of the data processing systems. Normally, while the writing and reading of data is being performed, interrupt requests are not sent to the microprocessor. If the microprocessor accepts an interrupt request, the writing or reading of data is interrupted and error in the data will occur. As will be described in detail later, the microprocessor cannot periodically reset a watchdog timer while the microprocessor is made not to receive any interrupt requests. If the microprocessor runs away while the microprocessor is made not to receive any interrupt requests, the watchdog timer circuit may not detect the runaway of the microprocessor. Hence, it is required to provide a watchdog timer circuit capable of detecting runaway of the microprocessor maintained in the state in which it is made not to receive any interrupt requests.
FIG. 1 is a block diagram of a data processing system including a watchdog timer circuit. The data processing system shown in FIG. 1 comprises a CPU (Central Processing Unit) 11, an interrupt controller 12, a timer 13, a floppy disk controller 16, a status register 17 and a floppy disk drive 18. The watchdog timer circuit built in the data processing system comprises a timer 13, a watchdog timer (WDT) 14, and a WDT control register 15 in addition to the CPU 11 and the timer 13.
The CPU 11 writes data, such as a binary one (a high (H) level signal), into the WDT control register 15 via a bus beforehand. The timer 13 periodically outputs a trigger signal to the interrupt controller 12. In response to the trigger signal, the interrupt controller 12 outputs an interrupt signal IRQ to the CPU 11. The CPU 11 counts how many times the interrupt signal has been repeatedly received, and periodically outputs a reset command to the WDT control register 15 via the bus. When the WDT control register 15 is reset, it outputs a clear signal, such as a binary zero (a low (L) level signal), to the watchdog timer 14. Hence, the watchdog timer 14 is reset before it reaches a predetermined counter value and starts to count pulses generated by a built-in clock generator (not shown).
When the issue of the reset command is delayed and the watchdog timer 14 reaches the predetermined counter value, the watchdog timer 14 outputs a watchdog timer alarm signal to the CPU 11. In response to the alarm signal, the CPU 11 stops operating.
Data can be written into the floppy disk driver 18 or read therefrom during a predetermined period of time (a predetermined time window) of a few us. In order to perform the writing or reading operation, the CPU 11 accesses the status register 17 by a polling process. The CPU 11 sends the floppy disk controller 16 information concerning the read/write condition which indicates whether the read or write operation should be performed and which area data should be written into the floppy disk drive 18 or read thereform. The floppy disk controller 16 reads one-byte data from the specified area and temporarily stores the read data in a built-in memory. Then, the floppy disk controller 16 writes status information expressed by a logic-high ready signal into the status register 17, and thereby the CPU 11 is informed that the floppy disk controller 16 is ready to handle data. The CPU 11 accesses the status register 17, and reads the contents thereof.
The CPU 11 handles data mounting to one sector by repeatedly performing the above-mentioned operation, and then specifies the next area. When the floppy disk controller 16 is ready to handle data again, it writes the logic-high ready signal into the status register 17. The CPU 11 notes the presence of the logic-high ready signal written into the status register 17, and accesses the floppy disk controller 16 again.
The above-mentioned read or write operation on one sector is repeatedly and successively carried out a predetermined number of times. If the read or write operation is interrupted during the read or write operation, errors will occur in the data written into or read from the floppy disk drive 18. Hence, the CPU 11 controls the interrupt controller 12 so that all interrupt requests are masked until the read or write operation is completed. During the read or write operation, the interrupt request from the timer 13 is not applied to the CPU 11, and hence the CPU 11 cannot manage the watchdog timer 14. Hence, the CPU 11 maintains the watchdog timer 14 in the initial or reset state while the floppy disk drive 18 is being accessed, and the watchdog timer 14 cannot detect whether or not the CPU 11 runs away during that time.